Cadence XCELIUM version 19.09.008 Hotfix Release

Cadence XCELIUM version 19.09.008 | 4.7 Gb
Product:Cadence XCELIUM
Version:MAIN (19.09.008) Hotfix Release *
Supported Architectures:x86_64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:Linux *
Size:4.7 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, has unveiled XCELIUM 19.09.008 is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Defects fixed in XCELIUM 19.09.008

2186425 CORE_SIM $fclose() does not close filehandle
2182856 HAL IGNDLY rule params are incorrect
AVSREQ-102540 GLS_SDF unconditional TC annotated on conditional TC get conditional and odd behavior
AVSREQ-100721 SIM_PERFORMANCE From 19.05-a001 xcelium evaluates 1’hx != 1’hx to 0
AVSREQ-102734 DMS_ELAB ams_manual_segragation error with part select
AVSREQ-99300 SV_CODEGEN xmelab: *F,CGFAIL: Code generation failed in ixcom compile.
AVSREQ-72489 MSIE_SIMULATION Xcelium has different results with and without MSIE
AVSREQ-102611 GLS_TIMING GLS Hold Timing Violation
AVSREQ-101037 DMS_SIM OOMR doesnt return to correct value to real variable in Xcelium 19.03
Cadence’s Xcelium Logic Simulationprovides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments.
Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.
Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Accelerating DFT Simulations with Xcelium Multi-Core
Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadence is a pivotal leader in electronic design and computational expertise,using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.

Supported Platforms and Operating Systems
Platform: lnx86
Architecture: x86_64
Supported OS: RHEL 6, RHEL 7.4
Installscape installation choices
PXCELIUMMAIN: Default, the full install of the XCELIUM MAIN release
PSSPECMAN: Use this for Specman product
PXCELIUM: Full install of the XCELIUM MAIN release
PXCELIUM_NO_GCC: Full install of the XCELIUM MAIN release without GCC installed
PXCELIUM_SIM_ONLY: XCELIUM MAIN simulator without Perspec, Indago, or Specman.

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